1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device that operates at a frequency controlled by a clock signal externally supplied, such as a synchronous dynamic random access memory (SDRAM).
2. Description of the Prior Art
A synchronous dynamic random access memory device (hereinafter referred to as a synchronous DRAM device) operates at an internal frequency (internal clock signal) controlled by an external clock signal supplied from the outside thereof. The frequency of the internal clock signal becomes lower (higher) as the frequency of the output clock signal becomes lower (higher). Generally, when the synchronous DRAM device is operated at the maximum operating frequency, a minimum amount of power is consumed. When the synchronous DRAM device is operated at a frequency lower than the maximum operating frequency, the operating frequency of the synchronous DRAM becomes lower than the maximum operating frequency and an increased amount of power is consumed. As the operating frequency (the frequency of the internal clock signal) becomes lower, an increased amount of power is consumed. As described above, the operating frequency (the frequency of the internal clock signal) is controlled by the external clock signal.